1. Field of the Invention
The present invention relates to the manufacture of integrated circuits on a substrate, and more particularly to a method for releasing the accumulation of charge on the wafer between etching steps comprising the etching process.
2. Background of the Invention
It is always difficult to maintain the stability of plasma discharge in a multi-step etching process. This is especially true for dielectric damascene etching applications. Charge will often accumulate on the wafer during a plasma oxide etching process. This accumulation of charge can prove detrimental in multi-etching step processes.
For example, when etching hole architectures, e.g., contact holes, via holes, etc., multiple etching steps are often required. In order to maintain stability throughout the process, the beginning and ending of each etching step must be tightly controlled. It has been noted that a smoother transition between etching steps in a multi-etching step process can be achieved by limiting the change in the total active gas flow used during the multiple etching steps. For example, it has been shown that by maintaining the principal etching gas substantially the same, with only the selective addition of polymer formers and oxygen containing gases, smoother transitions can be achieved. Again, it has been shown that the changes in total active gas flow should be kept below 30% in order to achieve such stability.
Logic circuitry fabricated on the substrate requires several layers of metallization with intervening inter-level dielectric layers. Small contact, or via holes need to be etched through each of the dielectric layers. The contact, or via holes are then filled with a conductor, composed typically of aluminum or copper. A horizontal wiring layer is often formed over one dielectric layer and then covered by another dielectric layer. The horizontal wiring and the underlying vias are often referred to as a single wiring layer. In a conventional process, not only are the contact, or via holes often filled with, e.g., aluminum or copper, but in addition, the contact, or via holes are also overfilled in order to form a thick planar layer over both the filled holes and the dielectric. Conventionally, a metal lithographic step then photographically defines a photo resist layer over the planar metal layers and etches be exposed metal into a network of conductive interconnects.
Via holes usually represent the smallest dimension defined in a dielectric etch. The smallest defined lateral dimension in a particular level is often referred to as the critical dimension (CD). Power levels typically require a larger via size, for example, 0.6 μm, while signal levels typically require smaller via sizes for example, 0.3 μm. These diameters grow smaller and smaller as processing capability is advanced. But as critical dimensions are reduced with advanced processing techniques, the need for stable etching is increased. Unfortunately, due to the accumulated charge that is created between etching steps and a multiple etching step process, it is difficult to achieve the process stability required to achieve acceptable failure rates.
For example, while the etching processes associated with holes typically are not halted as a result of charge accumulated on the wafer during an etching step, processing of trench-type architectures often suffer high halt rates as a result of the large accumulation of charge, which creates an effect similar to a capacitive effect.